Acoe201_lab1 (4).doc Apr 2026

The primary objective of this lab is to familiarize students with the hardware and software environment used throughout the semester to design and verify a simple CPU.

: Understanding the structure of Configurable Logic Blocks (CLBs) and programmable interconnects. ACOE201_Lab1 (4).doc

: Students typically use the Xilinx Spartan-3E Starter Kit, which features an FPGA, LEDs, buttons, and switches. The primary objective of this lab is to