The book describes on-chip decompression algorithms in Verilog, providing a realistic look at how these impact overall chip area and performance. Key Technical Coverage
Memory fault models, MBIST (Memory BIST) methods, and functional procedures. Digital System Test and Testable Design: Using ...
Verilog is used to describe the internal architectures of Built-In Self-Test (BIST) and Design for Testability (DFT) . This helps engineers evaluate hardware overhead and timing feasibility, which is critical for System-on-Chip (SoC) designs. MBIST (Memory BIST) methods
The text treats testing and testability as integral parts of the digital design process rather than afterthoughts. Digital System Test and Testable Design: Using ...